1. Field of the Invention
The present invention pertains to the field of video circuits. More particularly, this invention relates to an integrated circuit that employs adjustable gain control to perform video sync signal slicing.
2. Art Background
Video systems such as television receivers, video recorders, and computer display monitors commonly conform to one or more of a variety of video signal standards. One such video signal standard is the National Television Systems Committee (NTSC) standard which prevails in North America. Another such standard in the Phase Alternation Line-rate (PAL) standard which is common in Europe.
Both the NTSC and PAL standards define a series of sync pulses or a sync pulse train embedded within a video signal. Such a sync signal is typically provided to synchronize various portions of information contained in the video signal. For example, both the NTSC and PAL standards specify the 50% signal amplitude levels that occur on the leading edge of the horizontal sync pulse as a timing reference for color burst information contained in the video signal.
The video signals processed by video systems typically vary in amplitude due to of a variety causes. For example, atmospheric influences during video signal transmission typically cause variation in video signal amplitude. In addition, amplifier and cable attenuation and cable termination variation in cable transmission systems commonly cause amplitude variation in video signals. Theoretically, the 50% signal amplitude level of a horizontal sync pulse provides a suitable timing reference point in view of such amplitude variation.
As a consequence, prior video systems usually contain circuitry that detects such 50% signal amplitude levels on the horizontal sync pulse. Such a detection of the 50% signal amplitude levels of the horizontal sync pulse is commonly referred to as 50% video sync signal slicing.
One prior circuit for performing 50% video sync signal slicing employs sample and hold capacitors that store a sampled amplitude range of the horizontal sync pulse. However, such a circuit typically requires constant refresh by the horizontal sync pulses of the input video signal. If the input video signal is removed, the sample and hold capacitors typically discharge which may cause erroneous detections of the 50% slicing level. As a consequence, such a prior circuit includes a set of gates that isolate the sample and hold capacitors once the video input signal is removed. Unfortunately, such extra gates increases the cost of such circuitry. In addition, such extra gates consume the integrated circuit die space and thereby increase the overall cost of video systems that implement video sync signal slicing circuitry on an integrated circuit chip.